//////////////////////////////////////////////////////////////////////////////
// project: module for up_link
// name: 	up_link_top 
// designer:wanggj 
// data:	2014_06_05
// description: 
//			this module is used to communicate with pc,and interat whit down_link;
//			uart is used in the communication between pc and fpga;
//			baud is 115200 bps acquiescently;
//			the state of up_link use 1_step control;
//			if rx faill ,error_ul will be "1";
//			clk is 50MHz;
/////////////////////////////////////////////////////////////////////////////////
module up_link_top(	//input
					clk,
					nrst_ul,
					down_link_req,
					//a_o_addr,
					ack,
					rxd_ul,
					data_tx,
					//output
					up_link_req,
					error_uu,
					s_o_addr,
					rd,
					wr,
					addr,
					txd,
					data_rx,
					led
					//nstate_ul,state_tx
					);
					
//output	[1:0] nstate_ul,state_tx;					
parameter a_o_addr =	13'h1d0b;			
input				clk,
					nrst_ul,
					down_link_req,
					ack,
					rxd_ul;

input	[7:0]		data_tx;

output				up_link_req,
					error_uu,
					rd,
					wr,
					txd;
output  [3:0]       led;
output	[7:0]		data_rx;
output	[12:0]		addr,
					s_o_addr;

wire				en_tx,
					rdc,
					tdc,
					baud_set,
					error_ul,
					error,
					rd,
					wr,
					error_uu;		//error form uart or up_link_ctrl 
					
wire	[12:0]		s_o_addr,
					addr;
wire	[7:0]		data_rx;

reg					rxd_1,rxd;

parameter			BAUD_9600	=	1'b1,
					BAUD_19200	=	1'b0;
					
assign		error_uu = error || error_ul;
//assign		baud_set = BAUD_9600;
assign      s_o_addr =   13'h0000;

assign		baud_set	=	BAUD_19200;

always@(posedge clk)
begin
 rxd_1 <= rxd_ul;
end

always@(posedge clk)
begin
 rxd <= rxd_1;
end
					
up_link_ctrl u_ulc(	//input
					.clk(clk),
					.nrst(nrst_ul),
					.down_link_req(down_link_req),			
												//from down_link				
					//.a_o_addr(a_o_addr),		//from down_link
					.rdc(rdc),					//from uart
					.tdc(tdc),					//from uart
					.data_rx(data_rx),			//from uart
					.ack(ack),					//from sram_ctr
					
					//output
					.en_tx(en_tx),				//to uart
					.up_link_req(up_link_req),			
												//to down_link
					.error_ul(error_ul),
					.s_o_addr(s_o_addr),		//to down_link
					.addr(addr),				//address to sram_ctr
					.rd(rd),					//to sram_ctr
					.wr(wr),
					.led(led)
					//to sram_ctr
					//.nstate_ul(nstate_ul),
					//.state_tx(state_tx)
					);
					
uart u_uart	(	.clk(clk),
				.nrst(nrst_ul),
				.en_tx(en_tx),
				.rxd(rxd),
				.din(data_tx),
				.baud_set(baud_set),
				//out
				.txd(txd),
				.error(error),
				.rdc(rdc),
				.tdc(tdc),
				.data(data_rx)

				);
endmodule 
